Protel Design System Design Rule Check
PCB File : C:\avrprojects\WLED\pcb\WLED_my.PcbDoc
Date     : 04.08.2022
Time     : 19:42:45

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.5mm) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
   Violation between Silk To Solder Mask Clearance Constraint: (0.225mm < 0.254mm) Between Arc (86.578mm,84.463mm) on Top Overlay And Pad U2-1(87.503mm,83.438mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.225mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "POW_EXT" (78.334mm,31.725mm) on Bottom Overlay And Pad D1-1(75.565mm,32.772mm) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "R12" (71.196mm,39.268mm) on Top Overlay And Pad D1-2(75.565mm,39.872mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "C9" (70.51mm,59.995mm) on Top Overlay And Pad MAX4466-3(72.136mm,62.357mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "RESET" (70.104mm,76.454mm) on Top Overlay And Pad XX3-1(71.374mm,76.962mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (73.66mm,75.184mm)(74.422mm,75.184mm) on Top Overlay And Pad RESET-2(75.438mm,75.109mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.195mm < 0.254mm) Between Text "R14" (75.184mm,72.263mm) on Top Overlay And Pad RESET-2(75.438mm,75.109mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.195mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (76.454mm,75.184mm)(77.216mm,75.184mm) on Top Overlay And Pad RESET-2(75.438mm,75.109mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.218mm < 0.254mm) Between Text "RESET" (70.104mm,76.454mm) on Top Overlay And Pad RESET-2(75.438mm,75.109mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.218mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (73.66mm,69.088mm)(74.422mm,69.088mm) on Top Overlay And Pad RESET-1(75.438mm,69.164mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (76.454mm,69.088mm)(77.216mm,69.088mm) on Top Overlay And Pad RESET-1(75.438mm,69.164mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (100.838mm,37.211mm)(103.122mm,37.211mm) on Top Overlay And Pad C7-2(99.822mm,36.609mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (96.522mm,37.211mm)(98.806mm,37.211mm) on Top Overlay And Pad C7-2(99.822mm,36.609mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (100.838mm,30.607mm)(102.27mm,30.607mm) on Top Overlay And Pad C7-1(99.822mm,31.209mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (97.372mm,30.609mm)(98.806mm,30.609mm) on Top Overlay And Pad C7-1(99.822mm,31.209mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.008mm < 0.254mm) Between Text "U1" (92.508mm,51.897mm) on Top Overlay And Pad C3-1(93.623mm,54.356mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.008mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (98.298mm,60.579mm)(98.298mm,62.863mm) on Top Overlay And Pad C4-2(97.696mm,59.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (98.298mm,56.263mm)(98.298mm,58.547mm) on Top Overlay And Pad C4-2(97.696mm,59.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (91.694mm,57.115mm)(91.694mm,58.547mm) on Top Overlay And Pad C4-1(92.296mm,59.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (91.696mm,60.579mm)(91.696mm,62.013mm) on Top Overlay And Pad C4-1(92.296mm,59.563mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "R7" (106.921mm,76.111mm) on Top Overlay And Pad R6-1(107.72mm,77.978mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (84.582mm,42.926mm)(86.866mm,42.926mm) on Top Overlay And Pad C2-2(83.566mm,43.528mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (80.266mm,42.926mm)(82.55mm,42.926mm) on Top Overlay And Pad C2-2(83.566mm,43.528mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (84.582mm,49.528mm)(86.016mm,49.528mm) on Top Overlay And Pad C2-1(83.566mm,48.928mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (81.118mm,49.53mm)(82.55mm,49.53mm) on Top Overlay And Pad C2-1(83.566mm,48.928mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (90.703mm,63.678mm) on Top Overlay And Pad C5-1(93.496mm,64.897mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (106.921mm,84.366mm) on Top Overlay And Pad R3-1(107.72mm,86.487mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "R6" (106.909mm,80.061mm) on Top Overlay And Pad R1-1(107.72mm,82.296mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "C5" (92.697mm,66.967mm) on Top Overlay And Pad U2-10(92.128mm,67.938mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "C5" (92.697mm,66.967mm) on Top Overlay And Pad U2-11(94.128mm,67.938mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (112.649mm,64.135mm)(113.411mm,64.135mm) on Top Overlay And Pad PROG-2(114.427mm,64.21mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (115.443mm,64.135mm)(116.205mm,64.135mm) on Top Overlay And Pad PROG-2(114.427mm,64.21mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (112.649mm,70.231mm)(113.411mm,70.231mm) on Top Overlay And Pad PROG-1(114.427mm,70.155mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.156mm < 0.254mm) Between Track (115.443mm,70.231mm)(116.205mm,70.231mm) on Top Overlay And Pad PROG-1(114.427mm,70.155mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.156mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Track (106.604mm,44.009mm)(109.804mm,44.009mm) on Top Overlay And Pad VT1-1(109.154mm,44.534mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.04mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Track (106.604mm,44.009mm)(109.804mm,44.009mm) on Top Overlay And Pad VT1-3(107.254mm,44.534mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.04mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.04mm < 0.254mm) Between Track (106.604mm,42.859mm)(109.804mm,42.859mm) on Top Overlay And Pad VT1-2(108.204mm,42.334mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.04mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.063mm < 0.254mm) Between Region (0 hole(s)) Top Overlay And Pad Q1-3(78.258mm,33.534mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.063mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.063mm < 0.254mm) Between Region (0 hole(s)) Top Overlay And Pad Q1-1(78.258mm,38.094mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.063mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (86.383mm,32.539mm)(86.883mm,33.039mm) on Top Overlay And Pad Q1-4(85.558mm,35.814mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (86.383mm,39.089mm)(86.883mm,38.589mm) on Top Overlay And Pad Q1-4(85.558mm,35.814mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (75.006mm,48.666mm) on Top Overlay And Pad C8-1(76.303mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Text "XX1" (70.942mm,50.166mm) on Top Overlay And Pad C8-2(73.303mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (71.501mm,52.58mm)(71.501mm,54.864mm) on Top Overlay And Pad C9-2(72.103mm,55.88mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (71.501mm,56.896mm)(71.501mm,59.18mm) on Top Overlay And Pad C9-2(72.103mm,55.88mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (78.103mm,53.43mm)(78.103mm,54.864mm) on Top Overlay And Pad C9-1(77.503mm,55.88mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
   Violation between Silk To Solder Mask Clearance Constraint: (0.154mm < 0.254mm) Between Track (78.105mm,56.896mm)(78.105mm,58.328mm) on Top Overlay And Pad C9-1(77.503mm,55.88mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.154mm]
Rule Violations :47

Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
   Violation between Silk To Silk Clearance Constraint: (0.045mm < 0.254mm) Between Text "RESET" (70.104mm,76.454mm) on Top Overlay And Track (67.374mm,78.212mm)(72.374mm,78.212mm) on Top Overlay Silk Text to Silk Clearance [0.045mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "RESET" (70.104mm,76.454mm) on Top Overlay And Track (72.374mm,75.712mm)(72.374mm,78.212mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.01mm < 0.254mm) Between Text "R14" (75.184mm,72.263mm) on Top Overlay And Track (79.161mm,72.918mm)(84.161mm,72.918mm) on Top Overlay Silk Text to Silk Clearance [0.01mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R14" (75.184mm,72.263mm) on Top Overlay And Track (79.161mm,72.918mm)(79.161mm,75.418mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R14" (75.184mm,72.263mm) on Top Overlay And Track (77.216mm,69.088mm)(77.216mm,75.184mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (92.508mm,51.897mm) on Top Overlay And Track (92.623mm,53.106mm)(92.623mm,55.606mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (92.508mm,51.897mm) on Top Overlay And Track (92.623mm,53.106mm)(94.623mm,53.106mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C3" (92.812mm,56.439mm) on Top Overlay And Track (92.546mm,56.263mm)(98.298mm,56.263mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R7" (106.921mm,76.111mm) on Top Overlay And Track (106.72mm,76.728mm)(111.72mm,76.728mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.012mm < 0.254mm) Between Text "R7" (106.921mm,76.111mm) on Top Overlay And Track (106.72mm,76.728mm)(106.72mm,79.228mm) on Top Overlay Silk Text to Silk Clearance [0.012mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (90.703mm,63.678mm) on Top Overlay And Track (92.496mm,63.647mm)(92.496mm,66.147mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (90.703mm,63.678mm) on Top Overlay And Track (92.496mm,63.647mm)(94.496mm,63.647mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R1" (106.921mm,84.366mm) on Top Overlay And Track (106.72mm,85.237mm)(111.72mm,85.237mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.012mm < 0.254mm) Between Text "R1" (106.921mm,84.366mm) on Top Overlay And Track (106.72mm,85.237mm)(106.72mm,87.737mm) on Top Overlay Silk Text to Silk Clearance [0.012mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R6" (106.909mm,80.061mm) on Top Overlay And Track (106.72mm,81.046mm)(111.72mm,81.046mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R6" (106.909mm,80.061mm) on Top Overlay And Track (106.72mm,81.046mm)(106.72mm,83.546mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R11" (109.296mm,67.081mm) on Top Overlay And Track (112.649mm,64.135mm)(112.649mm,70.231mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "XX1" (70.942mm,50.166mm) on Top Overlay And Track (72.303mm,49.55mm)(72.303mm,52.05mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.171mm < 0.254mm) Between Text "XX1" (70.942mm,50.166mm) on Top Overlay And Track (72.303mm,52.05mm)(74.303mm,52.05mm) on Top Overlay Silk Text to Silk Clearance [0.171mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C1" (75.006mm,48.666mm) on Top Overlay And Track (75.303mm,49.55mm)(77.303mm,49.55mm) on Top Overlay Silk Text to Silk Clearance [0mm]
   Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.254mm) Between Text "C8" (72.492mm,52.883mm) on Top Overlay And Track (71.501mm,52.58mm)(77.253mm,52.58mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
   Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "MAX4466" (78.334mm,64.491mm) on Bottom Overlay And Text "Button_0" (74.93mm,65.532mm) on Bottom Overlay Silk Text to Silk Clearance [0mm]
Rule Violations :22

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 69
Waived Violations : 0
Time Elapsed        : 00:00:01